More on the TMS9900 CPU

 

The TMS9900 loads address 0000h and 0002h when power is applied, and it gets its workspace pointer (see previous post, the location in RAM where it will store its general purpose register file) and the starting PC value from those locations, but it also uses addresses 0000h through 0100h for interrupt and extended operation (think software interrupt) vectors, which, on a system with a general purpose operating system, almost certainly need to be in RAM. Contrast this to the 6502, which uses a zero page at 0000h through 0100h that usually must be in RAM, but loads its boot vector from FFFEh and FFFFh. This allows RAM to be located at address zero, and ROM the top of memory space. For the 9900, you almost need both RAM and ROM at address zero! The TIC Mk 0 (my first floating breadboard design) used a latch to redirect the ROM bank to the bottom of memory until the processor loads its first instruction, at which point it was shoved to the top of memory and RAM was addressed at address zero. However, the 9900 also has a LOAD line which, when brought low, causes the processor to load a workspace pointer and PC from addresses FFFCh and FFFEh; much more convenient! The Mk 1 is configured to latch LOAD low until the processor fetches its first instruction, and RAM is always low in memory while ROM is always high in memory.